This invention relates to a method of applying underfill encapsulant compounds that contain one or more expandable fillers and/or act as pressure sensitive adhesives. The encapsulants are used to protect and reinforce the interconnections between an electronic component and a substrate in a microelectronic device. Microelectronic devices contain multiple types of electrical circuit components, mainly transistors assembled together in integrated circuit (IC) chips, but also resistors, capacitors, and other components. These electronic components are interconnected to form the circuits, and eventually are connected to and supported on a carrier or a substrate, such as a printed wire board. The integrated circuit component may comprise a single bare chip, a single encapsulated chip, or an encapsulated package of multiple chips. The single bare chip can be attached to a lead frame, which in turn is encapsulated and attached to the printed wire board, or it can be directly attached to the printed wire board. These chips are originally formed as a semiconductor wafer containing multiple chips. The semiconductor wafer is diced as desired into individual chips or chip packages.
Whether the component is a bare chip connected to a lead frame, or a package connected to a printed wire board or other substrate, the connections are made between electrical terminations on the electronic component and corresponding electrical terminations on the substrate. One method for making these connections uses polymeric or metallic material that is applied in bumps to the component or substrate terminals. The terminals are aligned and contacted together and the resulting assembly is heated to reflow the metallic or polymeric material and solidify the connection.
During its normal service life, the electronic assembly is subjected to cycles of elevated and lowered temperatures. Due to the differences in the coefficient of thermal expansion for the electronic component, the interconnect material, and the substrate, this thermal cycling can stress the components of the assembly and cause it to fail. To prevent the failure, the gap between the component and the substrate is filled with a polymeric encapsulant, hereinafter called underfill or underfill encapsulant, to reinforce the interconnect material and to absorb some of the stress of the thermal cycling. Two prominent uses for underfill technology are for reinforcing packages known in the industry as chip scale packages (CSP), in which a chip package is attached to a substrate, and flip-chip packages in which a chip is attached by an array of interconnections to a substrate. Another function of the underfill is to reinforce the component against mechanical shock such as impact or vibration. This is especially important for durability in portable electronic devices such as cellular telephones and the like that may be expected to be accidentally dropped or otherwise stressed during use.
In conventional capillary flow underfill applications, the underfill dispensing and curing takes place after the reflow of the metallic or polymeric interconnect. In this procedure, flux is initially applied on the metal pads on the substrate. Next, the chip is placed on the fluxed area of the substrate, on top of the soldering site. The assembly is then heated to allow for reflow of the solder joint. At this point, a measured amount of underfill encapsulant material is dispensed along one or more peripheral sides of the electronic assembly and capillary action within the component-to-substrate gap draws the material inward. After the gap is filled, additional underfill encapsulant may be dispensed along the complete assembly periphery to help reduce stress concentrations and prolong the fatigue life of the assembled structure. The underfill encapsulant is subsequently cured to reach its optimized final properties. A drawback of capillary underfill is that its application requires several extra steps and is thus not economical for high volume manufacturing.
Recently, attempts have been made to streamline the process and increase efficiency by the use of no-flow underfill and coating the no-flow underfill directly on the assembly site before the placement of the component on that site. After the component is placed it is soldered to the metal connections on the substrate by passing the entire assembly through a reflow oven. During the process the underfill fluxes the solder and metal pads to form the interconnect joints between the interconnect, the substrate and the underfill. One limitation of the no-flow underfill process is that the substrate and components must be pre-dried to avoid excessive voiding within the underfill that will lead to solder extrusion that ultimately may create a short-circuit to another connection. Thus, the substrates must be dried before assembly and then stored in dry storage. This process is unwieldy for high volume manufacturers.
In order to be useful as a pre-applied underfill encapsulant, the underfill must have several important properties. First, the material must be easy to apply uniformly so that the entire assembly has a consistent coating. The underfill encapsulant must be either B-stageable, which means that the underfill must be solidified after its placement on a component to provide a smooth, non-tacky coating with minimal residual solvent, or capable of being formed into a film. Further, there is often great difficulty during manufacturing in uniformly applying conventional underfill materials.
The B-stage process usually occurs at a temperature lower than about 150° C. without prematurely curing the underfill encapsulant. The final curing of the underfill encapsulant must be delayed until after the solder fluxing (in the situation that solder is the interconnect material) and interconnection, which occurs at a temperature of 183° C. in the case of tin/lead eutectic solder. The final curing of the underfill should occur rapidly after the solder bump flow and interconnection. During this final attachment of the individual chips to a substrate, the underfill encapsulant must flow in order to enable fillet formation and provide good adhesion between the chip, or chip passivation layer, the substrate, or the solder mask, and the solder joints.